Cypress CY7C1422BV18 Manuel D’Utilisation
CY7C1422BV18, CY7C1429BV18
CY7C1423BV18, CY7C1424BV18
CY7C1423BV18, CY7C1424BV18
Document #: 001-07035 Rev. *D
Page 2 of 30
Logic Block Diagram (CY7C1422BV18)
Logic Block Diagram (CY7C1429BV18)
2M
x 8 Array
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Re
ad Add. Decode
Read Data Reg.
LD
Q
[7:0]
Reg.
Reg.
Reg.
8
16
8
NWS
[1:0]
V
REF
W
rite Add.
Deco
de
Write
Data Reg
Data Reg
8
8
21
8
R/W
LD
R/W
CQ
CQ
DOFF
2M
x 8 Array
Write
Data Reg
Data Reg
Control
Logic
C
C
8
2M
x 9 Arra
y
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
R
ead Add. Decode
Read Data Reg.
LD
Q
[8:0]
Reg.
Reg.
Reg.
9
18
9
BWS
[0]
V
REF
W
rite Add
. Decode
Write
Data Reg
Data Reg
9
9
21
9
R/W
LD
R/W
CQ
CQ
DOFF
2M
x 9 Arra
y
Write
Data Reg
Data Reg
Control
Logic
C
C
9