Intel 8XC251SP Manuel D’Utilisation
6-9
INTERRUPT SYSTEM
6.7
INTERRUPT PROCESSING
Interrupt processing is a dynamic operation that begins when a source requests an interrupt and
lasts until the execution of the first instruction in the interrupt service routine (see Figure 6-5).
Response time is the amount of time between the interrupt request and the resulting break in the
current instruction stream. Latency is the amount of time between the interrupt request and the
execution of the first instruction in the interrupt service routine. These periods are dynamic due
to the presence of both fixed-time sequences and several variable conditions. These conditions
contribute to total elapsed time.
lasts until the execution of the first instruction in the interrupt service routine (see Figure 6-5).
Response time is the amount of time between the interrupt request and the resulting break in the
current instruction stream. Latency is the amount of time between the interrupt request and the
execution of the first instruction in the interrupt service routine. These periods are dynamic due
to the presence of both fixed-time sequences and several variable conditions. These conditions
contribute to total elapsed time.
Figure 6-5. The Interrupt Process
Both response time and latency begin with the request. The subsequent minimum fixed sequence
comprises the interrupt sample, poll, and request operations. The variables consist of (but are not
limited to): specific instructions in use at request time, internal versus external interrupt source
requests, internal versus external program operation, stack location, presence of wait states, page-
mode operation, and branch pointer length.
comprises the interrupt sample, poll, and request operations. The variables consist of (but are not
limited to): specific instructions in use at request time, internal versus external interrupt source
requests, internal versus external program operation, stack location, presence of wait states, page-
mode operation, and branch pointer length.
NOTE
In the following discussion, external interrupt request pins are assumed to be
inactive for at least four state times prior to assertion. In this chapter all
external hardware signals maintain some setup period (i.e., less than one state
time). Signals must meet V
inactive for at least four state times prior to assertion. In this chapter all
external hardware signals maintain some setup period (i.e., less than one state
time). Signals must meet V
IH
and V
IL
specifications prior to any state time
under discussion. This setup state time is not included in examples or calcula-
tions for either response or latency.
tions for either response or latency.
OSC
Ending Instructions
Push PC
A4153-01
State
Time
External
Interrupt
Request
Request
ISR
Latency
Response Time
Call ISR