Intel 8XC251SP Manuel D’Utilisation
8XC251SA, SB, SP, SQ USER’S MANUAL
11-2
11.2 ELECTRICAL ENVIRONMENT
The 8XC251Sx is a high-speed CHMOS device. To achieve satisfactory performance, its operat-
ing environment should accommodate the device signal waveforms without introducing distor-
tion or noise. Design considerations relating to device performance are discussed in this section.
See the device data sheet for voltage and current requirements, operating frequency, and wave-
form timing.
ing environment should accommodate the device signal waveforms without introducing distor-
tion or noise. Design considerations relating to device performance are discussed in this section.
See the device data sheet for voltage and current requirements, operating frequency, and wave-
form timing.
11.2.1 Power and Ground Pins
Power the 8XC251Sx from a well-regulated power supply designed for high-speed digital loads.
Use short, low impedance connections to the power (V
Use short, low impedance connections to the power (V
CC
and V
CC
2
) and ground (V
SS
, V
SS
1
, and
V
SS
2
) pins.
V
CC
2
is a secondary power pin that reduces power supply noise. V
SS
1
and V
SS
2
are secondary
ground pins that reduce ground bounce and improve power supply bypassing. The secondary
power and ground pins are not substitutes for V
power and ground pins are not substitutes for V
CC
and V
SS
. They are not required for proper de-
vice operation; thus, the 8XC251Sx is compatible with designs that do not provide connections
to these pins.
to these pins.
11.2.2 Unused Pins
To provide stable, predictable performance, connect unused input pins to V
SS
or V
CC
. Untermi-
nated input pins can float to a mid-voltage level and draw excessive current. Unterminated inter-
rupt inputs may generate spurious interrupts.
rupt inputs may generate spurious interrupts.
11.2.3 Noise Considerations
The fast rise and fall times of high-speed CHMOS logic may produce noise spikes on the power
supply lines and signal outputs. To minimize noise and waveform distortion follow good board
layout techniques. Use sufficient decoupling capacitors and transient absorbers to keep noise
within acceptable limits. Connect 0.01 µF bypass capacitors between V
supply lines and signal outputs. To minimize noise and waveform distortion follow good board
layout techniques. Use sufficient decoupling capacitors and transient absorbers to keep noise
within acceptable limits. Connect 0.01 µF bypass capacitors between V
CC
and each V
SS
pin. Place
the capacitors close to the device to minimize path lengths.
Multilayer printed circuit boards with separate V
CC
and ground planes help minimize noise. For
additional information on noise reduction, see Application Note AP-125, “Designing Microcon-
troller Systems for Electrically Noisy Environments.”
troller Systems for Electrically Noisy Environments.”