Intel 8XC251SP Manuel D’Utilisation
A-5
INSTRUCTION SET REFERENCE
Table A-7. New Instructions for the MCS
®
251 Architecture
Bin.
A5
x8
A5
x9
A5
xA
A5
xB
A5
xC
A5
xD
A5
xE
A5
xF
Src.
x8
x9
xA
xB
xC
xD
xE
xF
0
JSLE
rel
rel
MOV
Rm,@WRj+dis
Rm,@WRj+dis
MOVZ
WRj,Rm
WRj,Rm
INC R,#short (1)
MOV reg,ind
MOV reg,ind
SRA
reg
reg
1
JSG
rel
rel
MOV
@WRj+dis,Rm
@WRj+dis,Rm
MOVS
WRj,Rm
WRj,Rm
DEC R,#short (1)
MOV ind,reg
MOV ind,reg
SRL
reg
reg
2
JLE
rel
rel
MOV
Rm,@DRk+dis
Rm,@DRk+dis
ADD
Rm,Rm
Rm,Rm
ADD
WRj,WRj
WRj,WRj
ADD
reg,op2 (2)
reg,op2 (2)
ADD
DRk,DRk
DRk,DRk
3
JG
rel
rel
MOV
@DRk+dis,Rm
@DRk+dis,Rm
SLL
reg
reg
4
JSL
rel
rel
MOV
WRj,@WRj+dis
WRj,@WRj+dis
ORL
Rm,Rm
Rm,Rm
ORL
WRj,WRj
WRj,WRj
ORL
reg,op2
reg,op2
(2)
5
JSGE
rel
rel
MOV
@WRj+dis,WRj
@WRj+dis,WRj
ANL
Rm,Rm
Rm,Rm
ANL
WRj,WRj
WRj,WRj
ANL
reg,op2
reg,op2
(2)
6
JE
rel
rel
MOV
WRj,@DRk+dis
WRj,@DRk+dis
XRL
Rm,Rm
Rm,Rm
XRL
WRj,WRj
WRj,WRj
XRL
reg,op2
reg,op2
(2)
7
JNE
rel
rel
MOV
@DRk+dis,WRj
@DRk+dis,WRj
MOV
op1,reg (2)
op1,reg (2)
MOV
Rm,Rm
Rm,Rm
MOV
WRj,WRj
WRj,WRj
MOV
reg,op2
reg,op2
(2)
MOV
DRk,DRk
DRk,DRk
8
LJMP @WRj
EJMP @DRk
EJMP @DRk
EJMP
addr24
addr24
DIV
Rm,Rm
Rm,Rm
DIV
WRj,WRj
WRj,WRj
9
LCALL@WRj
ECALL @DRk
ECALL @DRk
ECALL
addr24
addr24
SUB
Rm,Rm
Rm,Rm
SUB
WRj,WRj
WRj,WRj
SUB
reg,op2
reg,op2
(2)
SUB
DRk,DRk
DRk,DRk
A
Bit
Instructions (3)
Instructions (3)
ERET
MUL
Rm,Rm
Rm,Rm
MUL
WRj,WRj
WRj,WRj
B
TRAP
CMP
Rm,Rm
Rm,Rm
CMP
WRj,WRj
WRj,WRj
CMP
reg,op2
reg,op2
(2)
CMP
DRk,DRk
DRk,DRk
C
PUSH op1 (4)
MOV DRk,PC
MOV DRk,PC
D
POP
op1
op1
(4)
E
F
NOTES:
1.
1.
R = Rm/WRj/DRk.
2.
op1, op2 are defined in Table A-8.
3.
4.
See Table A-12.