Intel 8XC251SP Manuel D’Utilisation
2-7
ARCHITECTURAL OVERVIEW
2.2.3
Interrupt Handler
The interrupt handler can receive interrupt requests from eleven sources: seven maskable sources
and the TRAP instruction. When the interrupt handler grants an interrupt request, the CPU dis-
continues the normal flow of instructions and branches to a routine that services the source that
requested the interrupt. You can enable or disable the interrupts individually (except for TRAP)
and you can assign one of four priority levels to each interrupt. See Chapter 6, “Interrupt System,”
for a detailed description.
and the TRAP instruction. When the interrupt handler grants an interrupt request, the CPU dis-
continues the normal flow of instructions and branches to a routine that services the source that
requested the interrupt. You can enable or disable the interrupts individually (except for TRAP)
and you can assign one of four priority levels to each interrupt. See Chapter 6, “Interrupt System,”
for a detailed description.
2.2.4
On-chip Code Memory
For 83C251SA (ROM) and 87C251SA (OTPROM/EPROM) devices, memory locations
FF:0000H–FF:1FFFH are implemented with 8-Kbytes of on-chip code memory. For 83C251SB
and 87C251SB devices, memory locations FF:0000H–FF:3FFFH are implemented with 16-
Kbytes of on-chip code memory.
FF:0000H–FF:1FFFH are implemented with 8-Kbytes of on-chip code memory. For 83C251SB
and 87C251SB devices, memory locations FF:0000H–FF:3FFFH are implemented with 16-
Kbytes of on-chip code memory.
Following a reset, the first instruction is fetched from location FF:0000H. For 80C251Sx (no
ROM/OTPROM/EPROM) devices, location FF:0000H is always in external memory.
ROM/OTPROM/EPROM) devices, location FF:0000H is always in external memory.
2.2.5
On-chip RAM
The 8XC251SA and 8XC251SB have 1-Kbyte of on-chip data RAM at locations 20H–41FH. The
8XC251SP and 8XC251SQ have 512 bytes of on-chip data RAM at locations 20H–21FH. These
RAM locations can be accessed with direct, indirect, and displacement addressing. Ninety-six of
these locations (20H–7FH) are bit addressable. An additional 32 bytes of on-chip RAM (00H–
1FH) provide storage for the four banks of registers R0–R7.
8XC251SP and 8XC251SQ have 512 bytes of on-chip data RAM at locations 20H–21FH. These
RAM locations can be accessed with direct, indirect, and displacement addressing. Ninety-six of
these locations (20H–7FH) are bit addressable. An additional 32 bytes of on-chip RAM (00H–
1FH) provide storage for the four banks of registers R0–R7.
2.3
ON-CHIP PERIPHERALS
The on-chip peripherals, which lie outside the core, perform specialized functions. Software ac-
cesses the peripherals via their special function registers (SFRs). The 8XC251Sx has four periph-
erals: the watchdog timer, the timer/counters, the programmable counter array (PCA), and the
serial I/O port.
cesses the peripherals via their special function registers (SFRs). The 8XC251Sx has four periph-
erals: the watchdog timer, the timer/counters, the programmable counter array (PCA), and the
serial I/O port.
2.3.1
Timer/Counters and Watchdog Timer
The timer/counter unit has three timer/counters, which can be clocked by the oscillator (for timer
operation) or by an external input (for counter operation). You can set up an 8-bit, 13-bit, or 16-
bit timer/counter, and you can program them for special applications, such as capturing the time
of an event on an external pin, outputting a programmable clock signal on an external pin, or gen-
erating a baud rate for the serial I/O port. Timer/counter events can generate interrupt requests.
operation) or by an external input (for counter operation). You can set up an 8-bit, 13-bit, or 16-
bit timer/counter, and you can program them for special applications, such as capturing the time
of an event on an external pin, outputting a programmable clock signal on an external pin, or gen-
erating a baud rate for the serial I/O port. Timer/counter events can generate interrupt requests.