Intel 8XC251SP Manuel D’Utilisation
5-1
CHAPTER 5
PROGRAMMING
The instruction set for the MCS
®
251 architecture is a superset of the instruction set for the
MCS
®
51 architecture. This chapter describes the addressing modes and summarizes the instruc-
tion set, which is divided into data instructions, bit instructions, and control instructions. Appen-
dix A, “Instruction Set Reference,” contains an opcode map and a detailed description of each
instruction. The program status words PSW and PSW1 are also described.
dix A, “Instruction Set Reference,” contains an opcode map and a detailed description of each
instruction. The program status words PSW and PSW1 are also described.
NOTE
The instruction execution times given in Appendix A are for code executing
from on-chip code memory and for data that is read from and written to on-
chip RAM. Execution times are increased by executing code from external
memory, accessing peripheral SFRs, accessing data in external memory, using
real time wait states, using RD#/WR#/PSEN# preprogrammed wait states, or
extending the ALE pulse.
from on-chip code memory and for data that is read from and written to on-
chip RAM. Execution times are increased by executing code from external
memory, accessing peripheral SFRs, accessing data in external memory, using
real time wait states, using RD#/WR#/PSEN# preprogrammed wait states, or
extending the ALE pulse.
For some instructions, accessing the port SFRs (Px, x = 3:0) increases the
execution time. These cases are noted individually in the tables in Appendix A.
execution time. These cases are noted individually in the tables in Appendix A.
5.1
SOURCE MODE OR BINARY MODE OPCODES
Source mode and Binary mode refer to the two ways of assigning opcodes to the instruction set
of the MCS 251 architecture. Depending on the application, one mode or the other may produce
more efficient code. The mode is established during device reset based on the value of the SRC
bit in configuration byte UCONFIG0. For information regarding the selection of the opcode
mode, see section 4.6, “Opcode Configurations (SRC).”
of the MCS 251 architecture. Depending on the application, one mode or the other may produce
more efficient code. The mode is established during device reset based on the value of the SRC
bit in configuration byte UCONFIG0. For information regarding the selection of the opcode
mode, see section 4.6, “Opcode Configurations (SRC).”
5.2
PROGRAMMING FEATURES OF THE MCS
®
251 ARCHITECTURE
The instruction set for MCS 251 microcontrollers provides the user with new instructions that ex-
ploit the features of the architecture while maintaining compatibility with the instruction set for
MCS 51 microcontrollers. Many of the new instructions operate on 8-bit, 16-bit, or 32-bit oper-
ands. (In comparison with 8-bit and 16-bit operands, 32-bit operands are accessed with fewer ad-
dressing modes.) This capability increases the ease and efficiency of programming MCS 251
microcontrollers in a high-level language such as C.
ploit the features of the architecture while maintaining compatibility with the instruction set for
MCS 51 microcontrollers. Many of the new instructions operate on 8-bit, 16-bit, or 32-bit oper-
ands. (In comparison with 8-bit and 16-bit operands, 32-bit operands are accessed with fewer ad-
dressing modes.) This capability increases the ease and efficiency of programming MCS 251
microcontrollers in a high-level language such as C.
The instruction set is divided into data (refer to section 5.3, “Data Instructions”), bits (see section
5.4, “Bit Instructions”), and control instructions (see section 5.5, “Control Instructions”). Data in-
structions process 8-bit, 16-bit, and 32-bit data; bit instructions manipulate bits; and control in-
structions manage program flow.
5.4, “Bit Instructions”), and control instructions (see section 5.5, “Control Instructions”). Data in-
structions process 8-bit, 16-bit, and 32-bit data; bit instructions manipulate bits; and control in-
structions manage program flow.