Freescale Semiconductor 56F8122 Manuel D’Utilisation
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
3
Preliminary
56F8322/56F8122 Block Diagram
Program Controller
and Hardware
Looping Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
56800E Core
Interrupt
Controller
4
IRQA
Data Memory
4K x 16 Flash
4K x 16 RAM
PDB
PDB
XAB1
XAB2
XAB2
XDB2
CDBR
SPI0 or
SCI1 or
SCI1 or
GPIOB
IPBus Bridge (IPBB)
Decoding
Peripherals
Peripherals
Peripheral
Device Selects
RW
Control
IPWDB
IPRDB
System Bus
Control
R/W Control
Memory
PAB
PAB
CDBW
CDBR
CDBW
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
V
CAP
V
DD
V
SS
V
DDA
V
SSA
4
2
4
4
RESET
6
Quad Timer C
or SCI0
or GPIOC
AD0
3
Quadrature
Decoder 0 or
Quad
Timer A or
GPIO B
FlexCAN or
GPIOC
2
4
2
3
PLL
Clock
Generator*
XTAL or GPIOC
EXTAL or GPIOC
System
Integration
Module
P
O
R
O
S
C
Clock
resets
PWM Outputs
Fault Inputs
PWMA or
SPI1 or
GPIOA
TEMP_SENSE
*Includes On-Chip
Relaxation Oscillator
VREF
COP/
Watchdog
AD1
3
Program Memory
16K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
56F8322/56F8122 General Description
Note: Features in italics are NOT available in the 56F8122 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 3-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
• FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 21 GPIO lines
• 48-pin LQFP Package