Fujitsu FR81S Manuel D’Utilisation
CHAPTER 27: UP/DOWN COUNTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
4.4. Counter Status Register (CSR0, CSR1)
The bit configuration of the counter status register is shown below.
This register is used to check the status of the up/down counter and control interrupt requests.
CSR0 : Address 0F77
H
(Access : Byte)
CSR1 : Address 0F87
H
(Access : Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CSTR
CITE
UDIE
CMPF
OVFF
UDFF
UDF1
UDF0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R(RM1),W
R(RM1),W
R(RM1),W
R,WX
R,WX
[bit7] CSTR : Count activation bit
This bit starts and stops the up/down counter.
Write value
Description
0
Stops the counting.
1
Starts the up/down counter.
[bit6] CITE : Compare result match interrupt enable bit
This bit sets whether or not to generate a compare result match interrupt request when the counter value
matches the value set in the reload compare register (RCR) (CMPF=1).
matches the value set in the reload compare register (RCR) (CMPF=1).
Write value
Description
0
Disables compare result match interrupt requests.
1
Enables compare result match interrupt requests.
MB91520 Series
MN705-00010-1v0-E
1023