Fujitsu FR81S Manuel D’Utilisation
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
23
Notes:
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When transmission FIFO is enabled, writing "0" to this bit is valid.
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When FBYTE (for transmission) is "0", writing "0" to this bit is prohibited.
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When this bit is "0", the change in the FSEL bit is prohibited.
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When "1" is set to this bit, it does not affect the operation.
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If a read-modify-write instruction is executed, "1" will be read.
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When it is setting value or less, writing "0" to this bit is prohibited.
[bit1] FTIE (Flag for Transmit Interrupt Enable): Transmission FIFO interrupt enable bit
It is an interrupt enable bit for transmission FIFO. If you set this bit to "1", an interrupt will be generated
when the FDRQ bit is "1".
[bit0] FSEL (FIFO SELect): FIFO selection bit
This bit is used to select transmission/reception FIFO.
When this bit is set to "0", FIFO1 is assigned as the transmission FIFO, and FIFO2, the reception FIFO.
When this bit is set to "1", FIFO2 is assigned as the transmission FIFO, and FIFO1, the reception FIFO.
Notes:
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This bit will not be cleared by FIFO reset (FCL2, FCL1=1).
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When you change this bit, disable the FIFO operation (FCR:FE2, FE1=0) first.
MB91520 Series
MN705-00010-1v0-E
1336