Fujitsu FR81S Manuel D’Utilisation
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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[bit3, bit2] PAN (Protection Area Number)
Indicates the number of configurable protection areas that can be specified. This bit is read-only and
indicates the number of areas implemented in hardware.
PAN[1:0]
Number of memory protection areas implemented
00
Reserved
01
8 areas
10
12 areas
11
16 areas
[bit1] DEE (Data Access Error Interrupt Enable)
This bit permits interrupts to occur when a data access error occurs in areas where buffer operation is
enabled. If a data access error occurs in an area where buffer operation is permitted while this bit is enabled,
a data access error interrupt occurs. At this time, the address where the error occurred is stored in the data
access error address register (DEAR), and the details of the access are stored in the data access error status
register (DESR). If interrupts are disabled, the above registers are updated only.
DEE
Data access error interrupt enabled
0
Data access error interrupt disabled (Initial value)
1
Data access error interrupt enable
[bit0] MPE (Memory Protection Unit Enable)
This bit is for enabling the memory protection function. If the memory protection function is disabled,
buffering is configured as disabled for accesses to all areas.
MPE
Memory protection function
0
Memory protection function disabled (Initial value)
1
Memory protection function enabled
MB91520 Series
MN705-00010-1v0-E
127