Fujitsu FR81S Manuel D’Utilisation
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
327
8.2.4. I
2
C Bus Error
If a stop condition or (repeated) start condition is detected during data transmission/reception over the I
2
C
bus, it is treated as a bus error.
Bus Error Occurrence Condition
A bus error sets the IBCR:BER bit to "1" in one of the following conditions:
-
Detection of a (repeated) start or stop condition during the transfer of the first byte
-
Detection of a (repeated) start or stop condition at the second to ninth (acknowledge) bits of the data
Bus Error Operation
If the interrupt flag (IBCR:INT) becomes "1" due to transmission or reception, check the IBCR:BER bit. If
the IBCR:BER bit is "1", perform error handling. The IBCR:BER bit is cleared by writing "0" to the
IBCR:INT bit.
A bus error sets the IBCR:INT bit to "1", but does not bring the I
2
C bus to a wait state by setting SCL to
"L".
MB91520 Series
MN705-00010-1v0-E
1640