Fujitsu FR81S Manuel D’Utilisation
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
360
Figure 8-35 Master Reception interrupt (3)-when FIFO is Enabled
(SSR:DMA="0", IBCR:WSEL="0", IBCR:ACKE="0", IBSR:RSA="0")
S Slave Address R ACK Data ACK Data ACK Data NACK P or Sr
△▲
①
S: Start condition
R: Data direction bit (Read direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
(1) Generation of interrupt by TDRE="1":
- Sets MSS="0", MSS="1" or SCC="1" after reading all data from reception FIFO
Figure 8-36 Master Reception interrupt (4)-when FIFO is Enabled
(SSR:DMA="0", IBCR:WSEL="1", IIBSR:RSA="0")
S Slave Address R ACK Data ACK Data ACK Data NACK P or Sr
△ ▲
①
S: Start condition
R: Data direction bit (Read direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
(1) Generation of interrupt by TDRE="1":
- Sets "0" to ACKE and sets MSS="0" or MSS="1", and SCC="1" after reading all data
from reception FIFO
Figure 8-37 Master Reception interrupt (1)-when FIFO is Disabled
(SSR:DMA="1", IBCR:WSEL="0", IBSR:RSA="0")
S Slave Address R ACK Data ACK Data ACK Data NACK P or Sr
□ □ □ △▲
① ② ③ ④
S: Start condition
R: Data direction bit (Read direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
: Interrupt by TBIE= "1"
(1) An interrupt generated by slave address transmission + direction bit transmission +
acknowledgment reception
- the data of the dummy is written in the TDR register.
(2) An interrupt generated by 1byte reception + acknowledgment transmission
- the data of the dummy is written in the TDR register after reading reception data
(3) An interrupt generated by 1byte reception + acknowledgment transmission
- The data of the dummy is written in the TDR register after reading reception data
and set ACKE= "0"
(4) An interrupt generated by 1byte reception + acknowledgment transmission
- Set MSS = "0" or MSS = "1" and SCC = "1"
*: The TDRE bit is "1" upon the generation of the interrupt flag (INT)
MB91520 Series
MN705-00010-1v0-E
1673