Fujitsu FR81S Manuel D’Utilisation
CHAPTER 46: WORKFLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WORKFLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
Notes:
⋅
When writing in half-word, if the forth command (write data cycle) is written in the odd address, writing
is not performed correctly. Always write in even address.
⋅
In the first write command sequence, a single half-word data can be written. If you want to write multiple
data, issue one write command sequence for each data.
⋅
While security is ON, writing of flash is limited. See "5.9.4. Flash Access Restrictions When Security is
ON" for details.
Chip Erase Command
If the chip erase command is sent to the target sector six times in a row, all sectors of the flash memory can
be erased in one step. Once the sixth write has finished, the automatic program algorithm starts and the chip
erase operation is started. When the automatic erase algorithm is started, "0" is written to all of the cells in
the flash memory chip before erasing the entire chip, and there is no needs to write to the flash memory
before the chip erase to verify the margins (preprogramming). Furthermore, while verifying the margin,
there is no need to control the flash memory externally.
See "5.6 Chip Erase Command" for details on the actual operation.
MB91520 Series
MN705-00010-1v0-E
1992