Fujitsu FR81S Manuel D’Utilisation
CHAPTER 5: CLOCK
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
Figure 3-5 Connection Diagram of Clock (3) Divider Control
Figure 3-6 Connection Diagram of Clock (4) CAN Prescaler Clock Generation
Figure 3-7 Connection Diagram of Clock (5) Watch/Power Management Clock Generation
Main clock (MCLK)
CAN prescaler clock
PLL clock (PLLCLK)
* Non spread spectrum clock
0
1
CAN prescaler clock selection unit
PLL/SSCG oscillation enables
(CSELR:PCEN)
1
0
CAN prescaler clock
selection
(CANPRE:CPCKS)
On chip bus clock (HCLK)
MCLK
(PMUCLK)
PMU clock
0
1
CCRTSELR:CSC
SBCLK
(WATCLK)
RTC clock
CCPMUCR0:FDIV
CCPMUCR1:GDIV
0
1
Main clock
(128 to 512division)
divider
(F-divider)
PMU clock
(1 to 32division)
divider
(G-divider)
Peripheral clock (PCLK2)
Source clock (SRCCLK)
Base clock
PLL clock (PLLCLK)
* Non spread spectrum clock
(DIVR0.DIVB)
1/1 to 1/8
Clock divider control unit
Peripheral clock divider control unit
(
PICD.PDIV)
1/1 to 1/16
Peripheral
clock (PCLK1)
(DIVR2.DIVP)
1/1 to 1/16
External bus clock (TCLK)
(DIVR1.DIVT)
1/1 to 1/8
On-chip bus clock (HCLK)
×1
CPU clock (CCLK)
×1
(SACR.M)
Selector
MB91520 Series
MN705-00010-1v0-E
169