Fujitsu FR81S Manuel D’Utilisation
CHAPTER 50: RAM DIAGNOSIS FUNCTION
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAM DIAGNOSIS FUNCTION
FUJITSU SEMICONDUCTOR CONFIDENTIAL
30
4.15. TEST End Address Register BACKUP-RAM : TAEARA
This section explains the bit structure of TEST End Address Register BACKUP-RAM.
TEST end address register (TAEARA) specifies the end address of RAM diagnosis and initialization for
Backup RAM.
•
TAEARA: Address 303C
H
(Access: Byte, Half-word, Word)
15
14
13
12
11
10
9
8
BIT
Reserved
ED10
ED9
ED8
0
1
0
1
1
1
1
1
Initial values
R0, W0
R0, W0
R0, W0
R0, W0
R0, W0
R/W
R/W
R/W
Attributes
7
6
5
4
3
2
1
0
BIT
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
1
1
1
1
1
1
1
1
Initial values
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attributes
[bit15 to bit11] Reserved
Reserved bit. These bits read out "0". At writing, write "0".
[bit10 to bit0] ED10 to ED0: RAM diagnosis end address bits
These bits are used to specify the address with which the RAM diagnosis and initialization end for Backup
RAM.
Note:
Setting of a value outside the Backup RAM area and a value that sets TASARA.ST10 to ST0 >
TAEARA.ED10 to ED0 is disabled.
Note:
The above-mentioned address is an offset of the word length.
The absolute address is calculated by adding the base address to the offset address where lower two bits
were added.
(Absolute address) = (0000_4000
H
) + (Offset address set with TAEARA + 2'b00)
MB91520 Series
MN705-00010-1v0-E
2151