Fujitsu FR81S Manuel D’Utilisation
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
82
Figure 5-24 Block Diagram (32-bit PWC Timer Operation)
32-bit mode
T32=0
ch.0
ch.1
T32=1
BT0DTBF
CKS
EGS
3
3
20
27
28
28
MDSE
CTEN
CTEN
MDSE
16
T32
OVIE
EDIE
BT1DTBF
16
IRQ0
IRQ1
Peripheral
clock
(PCLK)
Waveform to
be measured
(TIN signal)
Edge
detection
Edge
detection
Division
circuit
Count
enable
Activation
detection
Stop detection
Count
clock
Count
enable
Up counter
Clear
Overflow
Count
clock
Count
enable
Up counter
Clear
Overflow
BT0DTBF :
Base timer 0 x data buffer register
(BT0DTBF)
BT1DTBF :
Base timer 1 x data buffer register
(BT1DTBF)
Overflow
interrupt request
Measurement
completion
interrupt request
Interrupt
factor
generation
MB91520 Series
MN705-00010-1v0-E
715