Fujitsu FR81S Manuel D’Utilisation
CHAPTER 23: 32-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
[bit9, bit8] OVPn : Pulse width measurement over flag
OVPn
Explanation
0
The pulse width data value is maximum value FFFF_FFFF
H
or less.
1
The pulse width data value exceeds maximum value FFFF_FFFF
H
.
⋅
These bits show that the data stored in the input capture data register (IPCPn) have exceeded the maximum
value. Whenever an effective edge is detected and measured, these bits are updated.
* OVPn : The number of n corresponds to the channel number of the input capture.
MB91520 Series
MN705-00010-1v0-E
888