Fujitsu FR81S Manuel D’Utilisation
CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL
LOW-VOLTAGE DETECTION)
6. Notes
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
INTERNAL LOW-VOLTAGE DETECTION (INTERNAL POWER SUPPLY
LOW-VOLTAGE
DETECTION)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
6. Notes
This section provides notes on the internal low-voltage detection (internal power supply
low-voltage detection).
Operation of internal low-voltage detection
If the internal power supply voltage falls and the internal low-voltage detection flag in the device is set
(LVD:LVD_F="1"), internal reset is generated by the function of low-voltage detection reset. Thus, writing
and reading of the internal low-voltage detection register (LVD) in the device is not allowed.
The internal low-voltage detection circuit can operate even though the device is in its sleep mode, stop
mode, and watch mode, consuming a certain amount of current.
The internal low-voltage detection circuit can be set to operate/stop by a user.
Initial value of internal low-voltage detection flag (LVD:LVD_F)
The internal low-voltage detection flag is set to "1" immediately after power-on. The internal low-voltage
detection flag is cleared by external reset or by writing "0" to the LVD_F bit of the internal low-voltage
detection register (LVD).
Oscillation stabilization wait time
If the internal power supply voltage falls below the detection voltage level, it takes the oscillation
stabilization wait time after the internal low-voltage detection voltage recovers. For details, see
"CHAPTER: RESET".
Hysteresis of detection/reset release voltage
Since the detection voltage and reset release voltage exhibit hysteresis of 0.1V, the reset release voltage
becomes the set detection voltage + 0.1V. For example, when LVD: 0.9V ± 0.1V is set, the reset release
voltage becomes 1.0V ± 0.1V.
MB91520 Series
MN705-00010-1v0-E
1152