Fujitsu FR81S Manuel D’Utilisation
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
Address
Registers
Note
+0
+1
+2
+3
Base-addr + 24
H
IF1 data B register 1
(IF1DTB1)
IF1 data B register 2
(IF1DTB2)
Byte order:
Big Endian
bit[7:0]
bit[15:8]
bit[7:0]
bit[15:8]
Data[4]
Data[5]
Data[6]
Data[7]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 30
H
IF1 data A register 2
(IF1DTA2)
IF1 data A register 1
(IF1DTA1)
Byte order:
Little Endian
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Data[3]
Data[2]
Data[1]
Data[0]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 34
H
IF1 data B register 2
(IF1DTB2)
IF1 data B register 1
(IF1DTB1)
Byte order:
Little Endian
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
Data[7]
Data[6]
Data[5]
Data[4]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
Base-addr + 40
H
IF2 command request register
(IF2CREQ)
IF2 command mask register
(IF2CMSK)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
BUSY
Mess. No. [5:0] Reserved bits
See the
IF2CMSK.
Reset: 00
H
Reset: 01
H
Reset: 00
H
Reset: 00
H
Base-addr + 44
H
IF2 mask register 2
(IF2MSK2)
IF2 mask register 1
(IF2MSK1)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MXtd, MDir,
Msk[28:24]
Msk[23:16]
Msk[15:8]
Msk[7:0]
Reset: FF
H
Reset: FF
H
Reset: FF
H
Reset: FF
H
Base-addr + 48
H
IF2 arbitration register 2
(IF2ARB2)
IF2 arbitration register 1
(IF2ARB1)
bit[15:8]
bit[7:0]
bit[15:8]
bit[7:0]
MsgVal, Xtd,
Dir,ID[28:24]
ID[23:16]
ID[15:8]
ID[7:0]
Reset: 00
H
Reset: 00
H
Reset: 00
H
Reset: 00
H
MB91520 Series
MN705-00010-1v0-E
1704