Fujitsu FR81S Manuel D’Utilisation
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
Note:
PLL enters the status of the oscillation enable regardless of the value of this bit while communicating the MDI
in high-speed.
[bit5] MCEN (Main Clock ENable) : Main clock oscillation enable
This bit controls an oscillation circuit for main clock as follows.
MCEN
Oscillation control for main clock
0
Stop oscillation
1
Oscillate
(Initial value)
This bit cannot be rewritten when a main clock (MCLK) or PLL/SSCG clock (PLLSSCLK) is selected as the
source clock.
The oscillation circuit for main clock always stops in stop mode regardless of the value of this bit.
The main timer is cleared when this bit is set to "0".
Note:
The main clock enters the status of the oscillation enable regardless of the value of this bit while
communicating the MDI in low-speed.
[bit4 to bit2] (Reserved)
[bit1, bit0] CKS[1:0] (ClocK Select) : Source clock selection
These bits select the source clock (SRCCLK) as follows.
CKS
Source selection
00
Division of the main clock (MCLK) by 2(Initial value)
01
Division of the main clock (MCLK) by 2
10
PLL/SSCG clock (PLLSSCLK)
11
Sub clock (SBCLK)
MB91520 Series
MN705-00010-1v0-E
176