Fujitsu FR81S Manuel D’Utilisation
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
91
5.7.3. 32-bit Timer Mode Operation
This section explains the 32-bit timer mode operation.
This section explains the setting and operation for cascading 2 channels of a 16-bit PWC timer and using them
as a 32-bit PWC timer.
Overview
Using the T32 bit of the timer control register (BTxTMCR), 2 channels of a 16-bit PWC timer can be
cascaded and used as a 32-bit PWC timer.
In this mode, the even-numbered channel corresponds to the lower 16-bit operation, and the odd-numbered
channel corresponds to the upper 16-bit operation. Therefore, the up counter must be read in the order of the
lower 16 bits (even-numbered channel) → the upper 16 bits (odd-numbered channel).
Setting Procedure (Example)
To select the 32-bit timer mode, set the T32 bit of the base timer x timer control register (BTxTMCR) of the
even-numbered channel to "1". Also, set the T32 bit of the odd-numbered channel to "0". When setting 32-bit
timer mode, set the registers using the procedure shown below.
The register setting differs between even-numbered and odd-numbered channels. In this example, channel 0
and channel 1 are connected by cascading.
1. Specify ch.0 to reset mode by setting FMD2 to FMD0 bits of the base timer 0 timer control register
(BT0TMCR). (FMD2 to FMD0 = 000)
2. Select 16/32-bit PWC timer for ch.0 and ch.1 by setting the FMD2 to FMD0 bits of the base timer x
timer control register (BT0TMCR, BT1TMCR) of ch.0 and ch.1. (FMD2 to FMD0 = 100) At the same
time, select the 32-bit timer mode by setting the T32 bit of the base timer 0 timer control register
(BT0TMCR). (T32 = 1)
Note:
Rewrite the T32 bit while the operation of both of the even-numbered and odd-numbered channels are
stopped. Whether the counting operation is stopped can be checked by setting the CTEN bit of the timer
control register (BTxTMCR) to "0"(CTEN=0).
Operations
In the 32-bit timer mode, the counting operation is basically the same as in the 16-bit timer mode. However,
the counting operation conforms to the settings of the even-number channels, ignoring the settings of the
registers next to the odd-number channels.
⋅
Base timer x timer control register (BTxTMCR)
⋅
Base timer x status control register (BTxSTC)
This section explains the counting in the 32-bit timer mode.
1. If the 16/32-bit PWC timer operation is enabled using the CTEN bit of the timer control register
(BTxTMCR) (by setting CTEN = 1) of the even-numbered channel, the 32-bit PWC timer starts.
2. When a measurement start edge is detected in the input signal (TIN), the counting starts.
3. The up counter starts counting as a 32-bit counter with the even-number channel serving as the lower
16 bits and the odd-number channel as the upper 16 bits.
4. When a measurement end edge is detected in the input signal (TIN), the lower 16-bit data of the up
counter is stored in the data buffer register (BTxDTBF) of the even-numbered channel. Also, the upper
16-bit data is stored in the data buffer register (BTxDTBF) of the odd-numbered channel.
MB91520 Series
MN705-00010-1v0-E
724