Emerson ATCA-9305 Manuel D’Utilisation
Management Processor CPLD:
MPC8548 PLD Register
5-6
Register 5-9:
Reset Command 1 (0x24)
Reset Command 2
The write-only Reset Command 2 register forces one of several types of MPC8548 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-10:
Reset Command 2 (0x28)
Reset Command 3
The write-only Reset Command 3 register forces one of several types of Cavium 1 resets, as
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
shown below. A reset sequence is first initiated by writing a one to a single valid bit, then the
PLD performs that particular reset, and the bit is automatically cleared.
Register 5-11:
Reset Command 3 (0x2C)
Bits:
Function:
Description:
7
WBR
Reset the Whole Board
6
PQCR
Reset the MPC8548 Complex
5
CAV1CR
Reset the Cavium CN5860 1 Complex
4
CAV2CR
Reset the Cavium CN5860 2 Complex
3
SWICR
Reset the switch BCM5680x Complex
2
I2C R
Reset the I2C on the MPC8548
1
RTMR
Reset the (optional) RTM
0
reserved
Bits:
Function:
Description:
7
PQHR
MPC8548 Hardware Reset
6
PQSR
MPC8548 Software Reset
5
PQDR
MPC8548 DDR SDRAM Reset
4
PQF
MPC8548 Flash reset
3
NANDR
MPC8548 NAND flash Reset
2
NANDWR
MPC8548 NAND flash Warm Reset
1
reserved
0
reserved
Bits:
Function:
Description:
7
CAV1R
Cavium 1 Reset
6
CAV1PR
Cavium 1 PCI Reset
5
CAV1DR
Cavium 1 DDR SDRAM Reset
4
CAV1F
Cavium 1 4 MB Flash (Cavium local bus) reset
3
CAV1M1
Cavium 1 MIP1 reset
2
CAV1M2
Cavium 1 MIP2 reset