Emerson ATCA-9305 Manuel D’Utilisation
Management Processor CPLD:
MPC8548 PLD Register
5-14
IPMP/IPMC GPIO Control
This register provides access (if required) to signals between the KSL CPLD and the IPMP, as
well as to signals between the KSL CPLD and the IPMC. The lower two bits can request
request the power down of a Cavium core from the sticky reset register.
well as to signals between the KSL CPLD and the IPMC. The lower two bits can request
request the power down of a Cavium core from the sticky reset register.
Register 5-27:
IPMP/IPMC GPIO Control (0x8C)
LPC Bus Control
This is the control register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU.
controller from the management CPU.
Register 5-28:
LPC Bus (0xD0)
LPC Data
This is the data register for the 4-bit LPC bus. It allows for communication with the IPMC
controller from the management CPU. This register provides the data to be sent or received,
depending upon the commands given in the control register.
controller from the management CPU. This register provides the data to be sent or received,
depending upon the commands given in the control register.
Bits:
Function:
Description:
7
IPMC2KSL4
Input only
6
IPMC2KSL3
5
IPMC2KSL2
4
IPMC2KSL1
3
IPMP2KSL4
Output only
2
IPMP2KSL3
Output only
1
IPMP2KSL2
Power-down signal for Cavium 2 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
0
IPMP2KSL1
Power-down signal for Cavium 1 (output)
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
Assert high to shut down the core. The sticky Cavium reset also
causes this to be asserted.
Bits:
Function:
Description:
7
LPCIE
LPC Interrupt Enable
6
LPCS
LPC State (internal use only)
5
4
3
2
4
3
2
LPCIOE
LPC I/O Error
1
SYNCE
SYNC Error
0
SYNCT
SYNC Time-out