Emerson 752I Manuel D’Utilisation
i-1
Index
A
acronyms
B
binary download format
block diagram
CPU reset
general system
IIC interface
IPMB connections
monitor power-up
system controller
board configuration registers, CPLD
boot commands, monitor
C
cable, console
cache, CPU memory
caution statements
PTMC and PTCC compatibility
setting the CPU configuration
register
register
writes to monitor area
circuit board dimensions
compatibility issues, CT bus
compliance
component map
bottom
jumpers, fuse, and switch
top
configuration registers, CPLD
connectors
cPCI
cPSB
J1
J2
J21-J24
J3
J4
J5
JTAG/COP
P1
PTMC
console serial port
contents, table of
CPU
block diagram
cache memory
exceptions
features
floating-point exception mode
initialization
memory map
CT bus interface
clocking model
compatibility types
direction control registers
local CT bus bit swapping
option 1
option 2
option overview
PICMG 2.15 Configuration 2
customer support
technical support
E
environment parameter commands,
monitor
monitor
environment variables
equipment for setup
error, parity
ESD prevention
Ethernet
address
Emerson identifier
interfaces
status LEDs
F
features
Hot Swap
IPMI
system controller
figures, list of
Flash commands, monitor
front panel
fuse locations
G
geographical addressing
GPIO signals
H
H.110
technical reference
HID registers
Hot Swap
I
ID select, PCI
IIC interface
installation of the board
interrupts
CPLD
interrupts, PCI
IPMI interface
J
JTAG/COP, pin assignments
jumpers
L
L2 cache
LEDs
bottom side locations
RMII PHY devices
M
machine state register (MSR)
mean time between failures (MTBF)
memory
commands, monitor
memory map
monitor
auto-repeat
basic operation
binary download format
boot commands
command reference
command syntax
command-line interface
environment parameter commands
environment variables
Flash commands
flash programming