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Emerson 752I Manuel D’Utilisation

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Processor:
 Processor Overview
4-2
Figure 4-1:
750GL Block Diagram
Physical Memory Map
752i monitor (see Chapter ) initializes the devices required to configure the 
memory map for the 750GL bus. The following figure shows the 750GL physical memory 
map.
Completion
System
Unit
Dispatch
BHT/BTIC
Instruction Fetch
Branch Unit
Control Unit
32KB I-Cache
with Parity
LSU
FPRs
Rename
Buffers
FPU
GPRs
Rename
Buffers
FXU2
FXU1
32KB D-Cache
with Parity
L2 Tags
with Parity
1MB
L2 Cache
w/ECC
Enhanced 60x
BIU