Emerson 752I Manuel D’Utilisation
Processor:
Processor Initialization
4-6
BTIC:
Branch Target Instruction Cache enable.
ABE:
Address Broadcast Enable (for cache ops, eieio, sync).
BHT:
Branch History Table enable.
NOOPTI:
No-op the dcbt/dcbst instructions.
Hardware Implementation Dependent 1 Register
The 750GL includes two phase-lock loops (PLL0 and PLL1), which allow the processor clock
frequency to be changed to one of the PLL frequencies via software control. The HID1 regis-
ter contains:
frequency to be changed to one of the PLL frequencies via software control. The HID1 regis-
ter contains:
• Fields that specify the frequency range of each PLL
• The clock multiplier of each PLL
• External or internal control of PLL0
• A bit to choose which PLL is selected (source of the processor clock at any given time):
Register 4-2:
750GL Hardware Implementation Dependent, HID1
PCE:
PLL External Configuration bits (read only).
PRE:
PLL External Range bits (read only).
PSTAT1:
PLL Status (not supported in DD1.x).
0 = PLL0 is the processor clock source
1 = PLL1 is the processor clock source
0 = PLL0 is the processor clock source
1 = PLL1 is the processor clock source
ECLK:
Enable the CLKOUT pin (set to 1).
PI0:
PLL 0 Internal configuration select.
0 = Select external configuration and range bits to control PLL0
1 = Select internal fields in HID1 to control PLL0
0 = Select external configuration and range bits to control PLL0
1 = Select internal fields in HID1 to control PLL0
PS:
PLL Select.
0 = Select PLL0 as source for processor clock
1 = Select PLL1 as source for processor clock
0 = Select PLL0 as source for processor clock
1 = Select PLL1 as source for processor clock
PC0:
PLL0 Configuration bits.
0
4
5
6
7
8
9
13
14
15
PCE
PRE
PSTAT1
ECLK
Reserved
PI0
PS
16
20
21
22
23
24
28
29
30
31
PC0
PR0
Res.
PC1
PR1
Res.