Emerson 752I Manuel D’Utilisation

 PCI Bus Control Signals

752i User’s Manual

PARITY. This is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is 
required by all PCI agents. This three-state signal is stable and valid one clock after the 
address phase, and one clock after the bus master indicates that it is ready to complete the 
data phase (either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains valid until 
one clock after the completion of the current data phase.

PARITY ERROR. This sustained three-state line is used to report parity errors during all PCI 
transactions.

POWER MANAGEMENT EVENT. This optional open-drain signal (pull-up resistor required) 
allows a device to request a change in the power state. Devices must be enabled by soft-
ware before asserting this signal. (The Katana

752i does not support this signal.)

PRESENT. When grounded, this signal indicates to a carrier that a PMC module is installed. 
(The Katana

752i does not support this signal.)

RESET OUTPUT. This optional output signal may be used to support another source. To 
avoid reset loops, do not use RST* to generate RESET_OUT*.

REQUEST. This output pin indicates to the arbiter that a particular master wants to use the 
bus.

RESET. The assertion of this input line brings PCI registers, sequencers, and signals to a con-
sistent state.

SYSTEMS ERROR. This open-collector output signal is used to report any system error with 
catastrophic results.

STOP. This is a sustained three-state signal used by the current target to request that the 
bus master stop the current transaction.

TARGET READY. This is a sustained three-state signal that indicates the target’s ability to 
complete the current data phase of the transaction.