Epson ARM720T Manuel D’Utilisation

The ARM720T processor EmbeddedICE-RT macrocell module provides integrated on-chip 

debug support for the ARM720T core. 
The EmbeddedICE-RT module is connected directly to the core and therefore functions on the 

virtual address of the processor before relocation by the FCSE PID. You program the 

EmbeddedICE-RT macrocell serially using the ARM720T processor TAP controller. 
Figure 9-5 shows the relationship between the core, EmbeddedICE-RT, and the TAP 

controller, showing only the signals that are pertinent to EmbeddedICE-RT.

Figure 9-5  The ARM720T core, TAP controller, and EmbeddedICE-RT macrocell

The EmbeddedICE-RT logic comprises the following:

Two real-time watchpoint units 

You can program one or both watchpoint units to halt the execution 

of instructions by the core. Execution halts when the values 

programmed into the EmbeddedICE-RT logic match the values 

currently appearing on the address bus, data bus, and various 

control signals. You can mask any bit so that its value does not 

affect the comparison. 
You can configure each watchpoint unit to be either a watchpoint 

(monitoring data accesses) or a breakpoint (monitoring instruction 

fetches). Watchpoints and breakpoints can be data-dependent.
For more details, see 

 on page 9-33.

ARM720-T

(Rev 4) core

EmbeddedICE-RT

macrocell

TAP