Epson ARM720T Manuel D’Utilisation

The ARM720T EmbeddedICE-RT macrocell contains a 

Debug Communication Channel

 (DCC) 

for passing information between the target and the host debugger. This is implemented as 

coprocessor 14.
The DCC comprises two registers, as follows:

DCC Control Register

A 32-bit register, used for synchronized handshaking between the 

processor and the asynchronous debugger. For more details, see 

DCC Data Register

A 32-bit register, used for data transfers between the debugger and 

the processor. For more details, see 

 on page 9-16.

These registers occupy fixed locations in the EmbeddedICE-RT memory map, as shown in 

Table 9-1 on page 9-12. They are accessed from the processor using MCR and MRC 

instructions to coprocessor 14.
The registers are accessed as follows:

By the debugger 

Through scan chain 2 in the usual way.

By the processor

Through coprocessor register transfer instructions.

The Domain Access Control Register is read-only and enables synchronized handshaking 

between the processor and the debugger. The register format is shown in Figure 9-6.

Figure 9-6  Domain Access Control Register

31

28 27

2 1 0

R

W

SB0

EmbeddedICE-RT version number