Epson ARM720T Manuel D’Utilisation
9: Debugging Your System
9-26
EPSON
ARM720T CORE CPU MANUAL
9.16
Examining the core and the system in debug state
When the ARM720T processor is in debug state, you can examine the core and system state
by forcing the load and store multiples into the instruction pipeline.
Before you can examine the core and system state, the debugger must determine whether the
Before you can examine the core and system state, the debugger must determine whether the
processor entered debug state from Thumb state or ARM state, by examining bit 4 of the
EmbeddedICE-RT debug status register, as follows:
Bit 4 HIGH
The core has entered debug from Thumb state.
Bit 4 LOW
The core has entered debug from ARM state.
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DBGBREAK
Input
Table 9-6 Scan chain 1 cells (continued)
Number
Signal
Type