Epson ARM720T Manuel D’Utilisation

If a watchpointed access simultaneously causes a Data Abort, the ARM720T processor enters 

debug state in abort mode. Entry into debug is held off until the core changes into abort mode 

and has fetched the instruction from the abort vector.
A similar sequence follows when an interrupt, or any other exception, occurs during a 

watchpointed memory access. The ARM720T processor enters debug state in the mode of the 

exception. The debugger must check to see whether an exception has occurred by examining 

the current and previous mode (in the CPSR, and SPSR), and the value of the PC. When an 

exception has taken place, you are given the choice of servicing the exception before 

debugging.
Entry to debug state when an exception has occurred causes the PC to be incremented by three 

instructions rather than four, and this must be considered in return branch calculation when 

exiting debug state. For example, suppose that an abort occurs on a watchpointed access, and 

ten instructions have been executed to determine this eventuality. You can use the following 

sequence to return to program execution.

0 E1A00000 ; MOV R0, R0

1 E1A00000 ; MOV R0, R0

0 EAFFFFF0 ; B -16
This code forces a branch back to the abort vector, causing the instruction at that location to 

be refetched and executed.

After the abort service routine, the instruction that caused the abort, and 

watchpoint is refetched and executed. This triggers the watchpoint again and the 

ARM720T processor reenters debug state.

Entry into debug state using a debug request is similar to a breakpoint. However, unlike a 

breakpoint, the last instruction has completed execution and so must not be refetched on exit 

from debug state. Therefore, you can assume that entry to debug state adds three addresses 

to the PC and every instruction executed in debug state adds one address.
For example, suppose you have invoked a debug request, and decide to return to program 

execution straight away. You could use the following sequence:

0 E1A00000 ; MOV R0, R0

1 E1A00000 ; MOV R0, R0

0 EAFFFFFA ; B -6
This code restores the PC and restarts the program from the next instruction.

When a system speed access is performed during debug state, the value of the PC increases by 

three addresses. System speed instructions access the memory system and so it is possible for 

aborts to take place. If an abort occurs during a system speed memory access, the ARM720T 

processor enters abort mode before returning to debug state.
This scenario is similar to an aborted watchpoint, but the problem is much harder to fix 

because the abort was not caused by an instruction in the main program, and so the PC does 

not point to the instruction that caused the abort. An abort handler usually looks at the PC to 

determine the instruction that caused the abort and also the abort address. In this case, the 

value of the PC is invalid, but because the debugger can determine which location was being 

accessed, the debugger can be written to help the abort handler fix the memory system.