Epson ARM720T Manuel D’Utilisation

This manual contains one or more timing diagrams. The following key explains the 

components used in these diagrams. Any variations are clearly labeled when they occur. 

Therefore, no additional meaning must be attached unless specifically stated.

Key to timing diagram conventions

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within 

the shaded area at that time. The actual level is unimportant and does not affect normal 

operation.

This section lists publications by ARM Limited, and by third parties.
ARM periodically provides updates and corrections to its documentation. See 
http://www.arm.com

 for current errata sheets, addenda, and ARM Frequently Asked Questions.

This document contains information that is specific to the ARM720T processor. Refer to the 

following documents for other relevant information:

•

ARM Architecture Reference Manual

 (ARM DDI 0100)

•

AMBA Specification (Rev 2.0) 

(ARM IHI 0011)

•

ETM7 (Rev 1) Technical Reference Manual

 (ARM DDI 0158)

•

ARM7TDMI-S (Rev 4) Technical Reference Manual

 (ARM DDI 0234).

This section lists relevant documents published by third parties.

•

Standard Test Access Port and Boundary Scan Architecture

 (IEEE Std. 

1149.1.1990).

Figure 9-8 on page 9-19 is printed with permission IEEE Std. 1149.1-1990, IEEE Standard 

Test Access Port and Boundary-Scan Architecture Copyright 2001, by IEEE. The IEEE 

disclaims any responsibility or liability resulting from the placement and use in the described 

manner.

Clock

Bus stable

HIGH to LOW

Transient

Bus to high impedance

Bus change

HIGH/LOW to HIGH

High impedance to stable bus