Epson ARM720T Manuel D’Utilisation

This section contains examples of how to program the watchpoint unit to generate breakpoints 

and watchpoints. Many other ways of programming the watchpoint unit registers are possible. 

For example, simple range breakpoints can be provided by setting one or more of the address 

mask bits.
To make a watchpoint unit cause watchpoints (on data accesses):

1

Program its address value register with the address of the data access to be 

watchpointed.

2

Program the address mask register to 0x00000000.

3

Program the data value register only if you require a data-dependent watchpoint, 

that is, only if you have to match the actual data value read or written as well as 

the address. If the data value is irrelevant, program the data mask register to 
0xFFFFFFFF

 (all bits set). Otherwise program the data mask register to 

0x00000000

.

4

Program the control value register as follows:
PROT[0] 

Set.

HWRITE

Clear for a read.
Set for a write.

SIZE[1:0]

Program with the value corresponding to the appropriate data size.

5

Program the control mask register as follows:
PROT[0]

Clear.

HWRITE 

Clear.
Note:

You can set this bit if both reads and writes are to be 

watchpointed.

SIZE[1:0] 

Clear.
Note:

You can set these bits if data size accesses are to be 

watchpointed.

All other bits

Set.

6

If you have to make the distinction between User and non-User mode data accesses, 

program the PROT[1] bit in the control value and control mask registers 

accordingly.

7

If required, program the DBGEXT, RANGE, and CHAIN bits in the same way.

Only bit 0 of this 32 bit read/write register is used. It determines whether an abort exception 

entry was caused by a breakpoint, a watchpoint, or a real abort. The format is shown in 

Figure 9-14  Debug abort status register

Bit 0 is set when the ARM720T core takes a Prefetch or Data Abort as a result of a breakpoint 

or watchpoint. If, on a particular instruction or data fetch, both the Debug Abort and the 

external Abort signal are asserted, the external Abort takes priority, and the DbgAbt bit is not 

set. Once set, DbgAbt remains set until reset by the user. The register is accessed by MRC and 

MCR instructions. 

0

31:1