Epson ARM720T Manuel D’Utilisation
A: Signal Descriptions
ARM720T CORE CPU MANUAL
EPSON
A-1
A
Signal Descriptions
This chapter describes the interface signals of the ARM720T processor. It contains the
following sections:
A.1
AMBA interface signals
Table A-1 AMBA interface signals
Signal name
Type
Description
HCLK
Input
Bus clock. This is the only clock on the ARM720T processor.
HADDR[31:0]
Output
32-bit system address bus.
HTRANS[1:0]
Output
Indicates type of current transfer.
HBURST[2:0]
Output
Indicates burst length of current transfer.
HWRITE
Output
Indicates direction of current transfer.
HSIZE[2:0]
Output
Indicates size of current transfer.
HPROT[3:0]
Output
Protection control signals
HGRANT
Input
Bus transfer granted.
HREADY
Input
Indicates that the current transfer has finished.
HRESP[1:0]
Input
Indicates transfer status.
HWDATA[31:0]
Output
Write data bus.
HRDATA[31:0]
Input
Read data bus.
HBUSREQ
Output
Bus transfer request.
HLOCK
Output
Indicates locked access.
HCLKEN
Input
Bus clock enable.
HRESETn
Input
Global reset.