Epson ARM720T Manuel D’Utilisation

The debugger signal descriptions are shown in Table A-4.

Output

Test data out.
JTAG test data out signal.

Input

Test mode select.
JTAG test mode select signal.

a.

These signals are only active when scan chain 0 is selected.

Table A-4  Debugger signal descriptions 

Input

Breakpoint.
This signal enables external hardware to halt execution of the processor 
for debug purposes. When HIGH, this causes the current memory 
access to be breakpointed. If memory access is an instruction Fetch, the 
core enters debug state if the instruction reaches the Execute stage of 
the core pipeline. If the memory access is for data, the core enters the 
debug state after the current instruction completes execution. This 
enables extension of the internal breakpoints provided by the 
EmbeddedICE-RT module.
In most systems, this input is tied LOW.

Output

Communication receive full.
When HIGH, this signal denotes that the comms channel receive buffer 
contains data for the core to read.

Output

Communication transmit empty.
When HIGH, this signal denotes that the comms channel transmit buffer 
is empty.

Output

Debug acknowledge.
When HIGH, this signal denotes that the ARM is in debug state.

Input

Debug enable
A static configuration signal that disables the debug features of the 
processor when held LOW.
This signal must be HIGH to allow the EmbeddedICE Logic to function.

Input

Debug request.
This signal causes the core to enter debug state after executing the 
current instruction. This enables external hardware to force the core into 
debug state, in addition to the debugging features provided by the 
EmbeddedICE-RT Logic.
In most systems, this input is tied LOW.
DBGRQ must be deasserted on the same clock that DBGACK is 
asserted.

Input

External condition.
These signals allow breakpoints and watchpoints to depend on an 
external condition.

Table A-3  JTAG and test signal descriptions  (continued)