Epson ARM720T Manuel D’Utilisation

This chapter describes the programmer’s model for the ARM720T processor. It contains the 

following sections:

From the point of view of the programmer, the ARM720T processor can be in one of two states:

ARM state 

This executes 32-bit, word-aligned ARM instructions.

Thumb state 

This operates with 16-bit, halfword-aligned Thumb instructions. In 

this state, the PC uses bit 1 to select between alternate halfwords.

Transition between processor states does not affect the processor mode or the contents of the 

registers.

Entry into Thumb state can be achieved by executing a BX instruction with the state bit (bit 

0) set in the operand register.
Transition to Thumb state also occurs automatically on return from an exception, for example, 

Interrupt ReQuest

 (IRQ), 

Fast Interrupt reQuest

 (FIQ), UNDEF, ABORT, and 

SoftWare 

Interrupt

 (SWI) if the exception was entered with the processor in Thumb state.

Entry into ARM state happens:

•

On execution of the BX instruction with the state bit clear in the operand register.

•

On the processor taking an exception, for example, IRQ, FIQ, RESET, UNDEF, 

ABORT, and SWI. In this case, the PC is placed in the link register of the exception 

mode, and execution starts at the vector address of the exception.