Epson ARM720T Manuel D’Utilisation

Bits 12:10 

When read, this returns an Unpredictable value. When written, it 

Should Be Zero, or a value read from these bits on the same 

processor.

Using a read-write-modify sequence when modifying this register provides the 

greatest future compatibility.

V Bit 13 

Location of exception vectors: 
0 = low addresses 
1 = high addresses.
The value of the V bit reflects the state of the VINITHI external 

input, sampled while HRESETn is LOW.

Bits 31:14 

When read, this returns an Unpredictable value. When written, it 

Should Be Zero, or a value read from these bits on the same 

processor.

You must take care if the translated address differs from the untranslated address, because 

the instructions following the enabling of the MMU are fetched using no address translation. 

Enabling the MMU can be considered as a branch with delayed execution. 
A similar situation occurs when the MMU is disabled. The correct code sequence for enabling 

and disabling the MMU is given 

 on page 7-21.

 

•

When the MMU is disabled the Cache is disabled.

•

If the cache and write buffer are enabled when the MMU is not enabled, the results 

are Unpredictable.

Reading from CP15 Register 2 returns the pointer to the currently active first-level 

translation table in bits [31:14] and an Unpredictable value in bits [13:0]. The CRm and 

opcode_2 fields Should Be Zero when reading CP15 Register 2.
Writing to CP15 Register 2 updates the pointer to the currently active first-level translation 

table from the value in bits [31:14] of the written value. Bits [13:0] Should Be Zero. The CRm 

and opcode_2 fields Should Be Zero when writing CP15 Register 2. Translation Table Base 

Register format is shown in Figure 3-6.

Figure 3-6  Translation Table Base Register format

31

14 13

00

Translation base table

UNP/SBZ