Epson ARM720T Manuel D’Utilisation

In the instructions shown in Table 3-3, c7 is the preferred value for the CRn field, because it 

indicates a unified MMU.
Reading from CP15 Register 8 is undefined.
The Invalidate TLB single entry function invalidates any TLB entry corresponding to the 

Modified Virtual Address

 (MVA) given in Rd.

You can access two independent process identifier registers using Register 13:

•

•

Reading from CP15 Register 13 with opcode_2 = 0 returns the value of the 

Fast Context Switch 

Extension

 (FCSE) 

Process IDentifier

 (PID). FCSCE PID Register format is shown in 

Figure 3-10  FCSCE PID Register format

 

Only bits [31:25] are returned. The remaining 25 bits are Unpredictable.

Writing to CP15 Register 13 with opcode_2 = 0 updates the FCSE PID from the value in bits 

[31:25]. Bits [24:0] Should Be Zero. The FCSE PID is set to b0000000 on Reset.
The CRm and opcode_2 Should Be Zero when reading or writing the FCSE PID.

You must take care when changing the FCSE PID because the following instructions have 

been fetched with the previous FCSE PID. In this way, changing the FCSE PID has 

similarities with a branch with delayed execution. See 

 on page 2-15.

A 32-bit read/write register is provided to hold a Trace 

PROCess IDentifier

 (PROCID) up to 

32-bits in length visible to the ETM7. This is achieved by reading from or writing to the 

PROCID Register with opcode_2 set to 1. PROCID Register format is shown in Figure 3-11.

Figure 3-11  PROCID Register format

The PROCIDWR signal is exported to notify the ETM7 that the Trace PROCID has been 

written.

31

25 24

00

FCSE PID

UNP/SBZ

31

00

Trace PROCID