Epson ARM720T Manuel D’Utilisation
6: The Bus Interface
6-10
EPSON
ARM720T CORE CPU MANUAL
6.5.2
HRESP[1:0]
HRESP[1:0] is used by the slave to show the status of a transfer. The HRESP[1:0] encodings
are shown in Table 6-5.
For a full description of the slave transfer responses, see the
AMBA Specification (Rev 2.0)
.
6.6
Data buses
To enable you to implement an AHB system without the use of tristate drivers, separate 32-bit
read and write data buses are required.
6.6.1
HWDATA[31:0]
The write data bus is driven by the bus master during write transfers. If the transfer is
extended, the bus master must hold the data valid until the transfer completes, as indicated
by HREADY HIGH.
All transfers must be aligned to the address boundary equal to the size of the transfer. For
All transfers must be aligned to the address boundary equal to the size of the transfer. For
example, word transfers must be aligned to word address boundaries (that is
A[1:0] = b00), and halfword transfers must be aligned to halfword address boundaries
(that is A[0] = 0).
The bus master drives all byte lanes regardless of the size of the transfer:
The bus master drives all byte lanes regardless of the size of the transfer:
•
For halfword transfers, for example 0x1234, HWDATA[31:0] is driven with the
value 0x12341234, regardless of endianness.
•
For byte transfers, for example 0x12, HWDATA[31:0] is driven with the value
0x12121212
0x12121212
, regardless of endianness.
Table 6-5 Response encodings
HRESP[1:0]
Response
Description
b00
OKAY
When HREADY is HIGH, this response indicates that
the transfer has completed successfully.
The OKAY response is also used for any additional
cycles that are inserted, with HREADY LOW, prior to
giving one of the three other responses.
the transfer has completed successfully.
The OKAY response is also used for any additional
cycles that are inserted, with HREADY LOW, prior to
giving one of the three other responses.
b01
ERROR
This response indicates that a transfer error has
occurred and the transfer has been unsuccessful.
Typically this is used for a protection error, such as an
attempt to write to a read-only memory location.The
error condition must be signalled to the bus master so
that it is aware the transfer has been unsuccessful.
A two-cycle response is required for an error condition.
occurred and the transfer has been unsuccessful.
Typically this is used for a protection error, such as an
attempt to write to a read-only memory location.The
error condition must be signalled to the bus master so
that it is aware the transfer has been unsuccessful.
A two-cycle response is required for an error condition.
b10
RETRY
The RETRY response shows the transfer has not yet
completed, so the bus master should retry the transfer.
The master should continue to retry the transfer until it
completes.
A two-cycle RETRY response is required.
completed, so the bus master should retry the transfer.
The master should continue to retry the transfer until it
completes.
A two-cycle RETRY response is required.
b11
SPLIT
The transfer has not yet completed successfully. The
bus master must retry the transfer when it is next
granted access to the bus. The slave will request access
to the bus on behalf of the master when the transfer can
complete.
A two-cycle SPLIT response is required.
bus master must retry the transfer when it is next
granted access to the bus. The slave will request access
to the bus on behalf of the master when the transfer can
complete.
A two-cycle SPLIT response is required.