Renesas M16C/6NK Manuel D’Utilisation

Page de 340
Rev.1.10    Jul 01, 2005    page 165 of 318
REJ09B0124-0110
M16C/6N Group (M16C/6NK, M16C/6NM)
14. Serial I/O
Under development
This document is under development and its contents are subject to change.
Table 14.15  Registers to Be Used and Settings in Special Mode 2
Register
Bit
Function
UiTB 
(1)
0 to 7
Set transmission data
UiRB 
(1)
0 to 7
Reception data can be read
OER
Overrun error flag
UiBRG
0 to 7
Set a transfer rate
UiMR 
(1)
SMD2 to SMD0
Set to “001b”
CKDIR
Set this bit to “0” for master mode or “1” for slave mode
IOPOL
Set to “0”
UiC0
CLK1, CLK0
Select the count source for the UiBRG register
CRS
Invalid because the CRD bit = 1
TXEPT
Transmit register empty flag
CRD
Set to “1”
NCH
Select TXDi pin output format
CKPOL
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
UFORM
Set to “0”
UiC1
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS 
(2)
Select UART2 transmit interrupt cause
U2RRM 
(2)
,
Set to “0”
UiLCH, UiERE
UiSMR
0 to 7
Set to “0”
UiSMR2
0 to 7
Set to “0”
UiSMR3
CKPH
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
NODC
Set to “0”
0, 2, 4 to 7
Set to “0”
UiSMR4
0 to 7
Set to “0”
UCON
U0IRS, U1IRS
Select UART0 and UART1 transmit interrupt cause
U0RRM, U1RRM
Set to “0”
CLKMD0
Invalid because the CLKMD1 bit = 0
CLKMD1, RCSP, 7 Set to “0”
i = 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.