Cypress CY7C638xx Manuel D’Utilisation
CY7C63310, CY7C638xx
Document 38-08035 Rev. *K
Page 42 of 83
15.3 SPI Interface Pins
The SPI interface uses the P1.3–P1.6 pins. These pins are configured using the P1.3 and P1.4–P1.6 Configuration.
Table 15-4. SPI Mode Timing vs. LSB First, CPOL and CPHA
LSB First CPHA CPOL
Diagram
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
S C L K
SSE L
D AT A
X
X
M S B
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
L S B
S C L K
S S E L
X
X
D A T A
M S B
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
L S B
SC L K
SS E L
X
X
D A T A
M S B
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
L S B
SC L K
SSEL
DAT A
X
X
MS B
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
LS B
SC L K
SSEL
D AT A
X
X
MS B
B it 2
B it 3
B it 4
B it 5
B it 6
B it 7
L S B
SCLK
SSEL
X
X
DAT A
MSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
LSB
SCLK
SSEL
X
X
DAT A
MSB
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
LSB
SCLK
SSEL
DAT A
X
MSB
X
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
LSB