Omega Vehicle Security 1500 Manuel D’Utilisation
Registers, Data Formats, & Queries
Appendix D
D-16
NetScan User’s Manual
Bit
Location
Description
Set, Clear and Descriptive Information
DI01
Alarm
Set when the scanning device has sensed a valid alarm condition. The alarm is
cleared when the alarm condition no longer exists.
cleared when the alarm condition no longer exists.
DI02
Trigger
Detected
Set when the NetScan has detected the trigger condition and will be cleared when the
acquisition is complete or the trigger has been reconfigured.
acquisition is complete or the trigger has been reconfigured.
DI03
Ready
Set when the NetScan is ready to process another command. It is cleared when the
NetScan is processing a command line. This bit should be examined with a serial poll
prior to issuing a new command line. This allows any detected errors to be traced to
the specific command line containing the error. If all the setup information for a
specific NetScan operation is included in one line, this bit also indicates when all
processing is done and the X command is completed. This ensures that the NetScan
is done processing all state changes before initiating any further activity.
NetScan is processing a command line. This bit should be examined with a serial poll
prior to issuing a new command line. This allows any detected errors to be traced to
the specific command line containing the error. If all the setup information for a
specific NetScan operation is included in one line, this bit also indicates when all
processing is done and the X command is completed. This ensures that the NetScan
is done processing all state changes before initiating any further activity.
DI04
Scan
Available
Set when at least 1 acquisition scan is available in the acquisition buffer to be read.
Cleared when there are no scans available in the buffer to be read.
Cleared when there are no scans available in the buffer to be read.
DI05
Message
Available
(MAV)
(MAV)
Set when the output queue is not empty. It is cleared when the output queue is empty.
This bit reflects whether any command responses are still in the output queue.
This bit reflects whether any command responses are still in the output queue.
DI06
Event Status
Register Bit
(ESB)
(ESB)
Reflects the logical OR of all the bits in the Event Status Register (ESR) ANDed with
their equivalent enable bits in the Event Status Enable (ESE) register. If this bit is set,
at least one bit in the ESR is set and has its corresponding enable bit in the ESE set.
The status command U0 can be issued to read the ESR. See the following for more
information on ESR and ESE.
their equivalent enable bits in the Event Status Enable (ESE) register. If this bit is set,
at least one bit in the ESR is set and has its corresponding enable bit in the ESE set.
The status command U0 can be issued to read the ESR. See the following for more
information on ESR and ESE.
DI08
Buffer
Overrun
Set if a buffer overrun occurs. It is cleared when the buffer becomes empty by either
reading out the contents of the buffer or performing a Reset (*B) of the buffer.
reading out the contents of the buffer or performing a Reset (*B) of the buffer.
Using Status Reporting Registers
As mentioned earlier the status reporting registers are organized in a hierarchical structure with the lower level
registers containing more general information and the higher level registers containing more detailed
information about particular events. In general, the lowest level register, the Status Byte Register (STB)
contains information that may require more immediate action from the controller in that events contained in this
register tend to be more time critical.
registers containing more general information and the higher level registers containing more detailed
information about particular events. In general, the lowest level register, the Status Byte Register (STB)
contains information that may require more immediate action from the controller in that events contained in this
register tend to be more time critical.
However, as mentioned earlier, other registers may access the STB via the ESB bit. This allows any condition
within the status reporting register hierarchy to have access to the STB and therefore Serial Poll and Service
Request functionality. The following is an example to show, in brief, how the status reporting register hierarchy
works. Notice that the clearing of the higher level registers cleared the bits in the lower level registers that were
associated with the root cause of the condition.
within the status reporting register hierarchy to have access to the STB and therefore Serial Poll and Service
Request functionality. The following is an example to show, in brief, how the status reporting register hierarchy
works. Notice that the clearing of the higher level registers cleared the bits in the lower level registers that were
associated with the root cause of the condition.
PRINT#1,"N0 X N16 X" ‘ Configure ESB in the STB to be set when a Device Dependent
‘ Error occurs.
. ‘ Cause an error.
PRINT#1,"E?X"
‘ Query the ESC to determine the cause of the error
INPUT#1,A$
‘ Get the response
PRINT A$
‘ Screen shows E016.This is a calibration error
PRINT#1,"U2X"
‘ Query the CSR to determine the cause of the ‘ calibration error
INPUT#1, A$
‘ Get the response
PRINT A$
‘ Screen shows E002. This is a calibration Gain error
PRINT#1,"U0X"
‘ Now query the ESR (reading ESC should have cleared it)
INPUT#1, A$
‘ Get the response
PRINT A$
‘ Screen shows 000 — Device Dependent Error no longer there
PRINT#1,"U1X”
‘ Now query the STB.
INPUT#1, A$
‘ Get the response
PRINT A$
‘ Screen shows 4 — ESB bit no longer set (only Ready is set).