Emerson CC1000DM Manuel D’Utilisation
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P M C / P C I I N T E R F A C E
PCI Identification Values
3-11
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P C I I D E N T I F I C A T I O N V A L U E S
Each CC1000dm configuration has a unique set of identification values. The base
address for these values is determined by the CC1000dm’s location in the cPCI rack and
the baseboard. The standard PCI hex offsets are:
address for these values is determined by the CC1000dm’s location in the cPCI rack and
the baseboard. The standard PCI hex offsets are:
Vendor ID
00
16
Device ID
02
16
Subsystem Vendor ID
2C
16
Subsystem ID
2E
16
All of these values are two bytes wide (half-word). Please refer to the PLX PCI 6254
data book for more information. The following table lists the identification values for
the different CC1000dm configurations:
data book for more information. The following table lists the identification values for
the different CC1000dm configurations:
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J T A G H E A D E R S
Each processor PMC slot has a 10-pin debug header (see
). These headers are
located at JP1 (PMC1) and JP2 (PMC2) to provide easy access to the following signals
in
in
The signals for the JTAG header are defined as follows:
TCK:
Test Clock Input is clock state information and test data into and out of PMC slots dur-
ing the test access port (TAP) operation. Scan data is latched at the rising edge of this
signal.
ing the test access port (TAP) operation. Scan data is latched at the rising edge of this
signal.
Vendor
ID (hex):
ID (hex):
Device
ID (hex):
ID (hex):
Subsystem
Vendor ID (hex):
Vendor ID (hex):
Subsystem
Device ID (hex):
Device ID (hex):
PCI 6254 Bridge Mode:
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3388
20
–
–
Transparent
21
1223
3A
Non-transparent
Pin:
Signal:
Pin:
Signal:
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1
TCK
2
ground
3
TDO
4
5V (fused)
5
TMS
6
no connect
7
no connect
8
no connect
9
TDI
10
ground
Table 3-7:
PCI Identification Values
Table 3-8:
Debug Header Pin
Assignments (JP1, JP2)
Assignments (JP1, JP2)