Renesas SH7641 Manuel D’Utilisation

Section 17   Compare Match Timer (CMT) 

Rev. 4.00  Sep. 14, 2005  Page 512 of 982 

REJ09B0023-0400 

 

1 

0 

CKS1 

CKS0 

0 

0 

R/W 

R/W 

Clock Select 

These bits select the clock to be input to CMCNT from 
four internal clocks obtained by dividing the peripheral 
operating clock (P

φ). When the STR bit in CMSTR is 

set to 1, CMCNT starts counting on the clock selected 
with bits CKS1 and CKS0. 

00: P

φ/4 

01: P

φ/8 

10: P

φ/16 

11: P

φ/64 

Note:  *  Only 0 can be written, to clear the flag. 

 

Compare Match Counter (CMCNT ) 

CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with 
bits CKS1 and CKS0 in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting 
using the selected clock. 

When the value in CMCNT and the value in compare match constant register (CMCOR) match, 
CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. 

CMCNT is initialized to H'0000 by a power on reset, but is not initialized in standby mode. 

CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. 

CMCOR is initialized to H'FFFF by a power on reset, but is not initialized in standby mode.