Renesas SH7641 Manuel D’Utilisation

Section 21   A/D Converter 

 

 

Rev. 4.00  Sep. 14, 2005  Page 807 of 982 

 

 REJ09B0023-0400 

Typical operations when three channels in A/D0 (AN0 to AN2) are selected in multi mode are 
described next. Figure 21.3 shows a timing diagram for this example. 

1.  Multi mode is selected (MULTI = 1), channel group A/D0 is selected, analog input channels 

AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 

2.  When A/D conversion of the first channel (AN0) is completed, the result is transferred into 

ADDRA0. 

3.  Next, conversion of the second channel (AN1) starts automatically. 

4.  Conversion proceeds in the same way through the third channel (AN2). 

5.  When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 

and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI0 interrupt is requested at this 
time. 

 

Channel 0 (AN0)

operating

ADST

ADF

Channel 1 (AN1)

operating

Channel 2 (AN2)

operating

Channel 3 (AN3)

operating

ADDRA

ADDRB

ADDRC

ADDRD

Waiting

Waiting

Waiting

Waiting

Set*

Clear*

Clear

A/D conversion result 2

Waiting

Waiting

A/D conversion result 3

A/D conversion 1

Waiting

A/D conversion result 1

Transfer

A/D conversion 3

A/D conversion

A/D conversion 2

Note: *  Vertical arrows (   ) indicate instruction execution by software.