Emerson PME1 Manuel D’Utilisation
Index
(continued)
10002367-02
PmT1 and PmE1 User’s Manual
i-3
getTBU
HexToBin
InitBoard
InitFifo
Interact
invalidate_dcache
invalidate_icache
IsLegal
IsPowerUp
KBHit
LongAddrTest
Malloc
MaskInts
MemAdd
MemBase
MemReset
MemStats
MemTop
NvHkOffset
NvMonAddr
NvMonOffset
NvMonSize
NVOp
NVRamAcc
PingPongAddrTest
probe
put_c
put_d
putchar
ReAlloc
RKBHit
RotTest
RTxMT
Seed
setMSR
SetNotPowerUp
SetNvDefaults
SetUnExpIntFunct
StrCat
StrCmp
StrCpy
StrLen
TestSuite
time_delay
ToFifo
tx_empty
TxMT
UnMaskInts
VecInit
WordAddrTest
writeICTRL
xprintf
xsprintf
N
non-burst cycles
notation conventions
number bases for monitor arguments
numeric format
NVRAM default monitor configuration
P
P11/P12 signal descriptions
parity error signal, PCI
PASS/FAIL power-up diagnostic flags
PMC/PCI
bandwidth
base address registers
bus interface
deadlocked cycle
direct slave cycles
EEPROM control register
initialization
interrupts
local direct master cycles
overview
PCI bridge
phantom read
register map
retry timers
power requirements
power-up
errors
monitor sequence
power-up diagnostics
test commands
product ID
product repair
protection circuitry
protocols
HDLC
UART
R
RAM
dual port
overview
read cycle access time
receive clock (RCLK)
receive link (RLINK)
receive link clock (RLCLK)
receive serial (RSER)
receive sync (RSYNC)
references and manuals
register map for PCI9060ES
register monitor commands
registers
BCR
BRGC
local configuration
PCI configuration
shared runtime
SICR
SIMODE
regulatory certifications
request signal, PCI
reset
monitor sequence
PCI signal
returning boards
RISC controller
RJ-45 jack
RoHS
S
S0-records
S1-S3 data records
S5 data records
S7-S9 termination and start address
records
records
screen messages
SDMA channels
serial and version numbers
serial I/O
baud rate
control from the monitor
overview
protocols
reference manuals
serial management controller (SMC)
serial number
SERR*
setup requirements
SICR register
SIMODE register
specifications