Emerson PMT1 Manuel D’Utilisation
PMC/PCI Interface:
PCI9060ES Initialization
10002367-02
PmT1 and PmE1 User’s Manual
7-7
Table 7-7:
PCI9060ES Bus Priority Control
As an example, a user could give priority to the Direct Slave device (PCI bus) by enabling the
BREQo timer and setting Direct Slave BREQo Delay Clocks to a value less than PCI Target
Retry Clocks. When a deadlock occurs, the BREQo timer expires and the PCI9060ES asserts
BREQo to the local bus master, forcing it to relinquish the bus and retry its cycle later. This
allows the Direct Slave cycle to complete.
BREQo timer and setting Direct Slave BREQo Delay Clocks to a value less than PCI Target
Retry Clocks. When a deadlock occurs, the BREQo timer expires and the PCI9060ES asserts
BREQo to the local bus master, forcing it to relinquish the bus and retry its cycle later. This
allows the Direct Slave cycle to complete.
Alternatively, a user could give priority to the Local Direct Master by disabling the BREQo
timer and setting PCI Target Retry Clocks to a nominal value. When a deadlock occurs, the
PCI target retry timer expires, forcing the Direct Slave device to relinquish the PCI bus and
retry its cycle later. This allows the Local Direct Master cycle to complete.
timer and setting PCI Target Retry Clocks to a nominal value. When a deadlock occurs, the
PCI target retry timer expires, forcing the Direct Slave device to relinquish the PCI bus and
retry its cycle later. This allows the Local Direct Master cycle to complete.
Note:
The factory default values favor the local bus during deadlocked cycles. Tune the timer values appropriately
for the system devices.
for the system devices.
Controlling Access Latency
When initializing the PCI9060ES, make sure that the retry timers are set to a value greater
than the maximum latency of the target device.
than the maximum latency of the target device.
For example, if the register value for PCI Target Retry Delay Clocks is 2
16
, a PCI master must
access the local bus and complete its cycle within 16 clocks. In this situation, however, the
Direct Slave cycle would seldom gain access because of the local bus acquisition latency.
(The Direct Slave device must wait for the CPU to finish its local I/O cycle and relinquish the
local bus.) Setting the Direct Slave BREQo Delay Clocks value too low has a similar effect on
Local Direct Master cycles.
Direct Slave cycle would seldom gain access because of the local bus acquisition latency.
(The Direct Slave device must wait for the CPU to finish its local I/O cycle and relinquish the
local bus.) Setting the Direct Slave BREQo Delay Clocks value too low has a similar effect on
Local Direct Master cycles.
Avoiding the PCI9060ES Phantom Read
As a default, Emerson configures the PCI9060ES to favor Local Direct Master cycles by
allowing retries only on Direct Slave cycles (see
allowing retries only on Direct Slave cycles (see
). This avoids a problem with the
PCI9060ES that can happen when a local bus master attempts to read from a PCI device and
a deadlocked cycle occurs that results in a BREQo to the local master. The PCI9060ES retries
the read cycle on the PCI bus and discards the data before the local bus master retries the
cycle. This phantom read (reading ahead) by the PCI9060ES affects target devices that
change their data or state upon access, such as FIFOs or other devices. (For example, some
devices de-assert their interrupts after a vector is read.) In these cases, the PCI9060ES phan-
tom read access can result in a bus error or bad data upon subsequent read cycles.
a deadlocked cycle occurs that results in a BREQo to the local master. The PCI9060ES retries
the read cycle on the PCI bus and discards the data before the local bus master retries the
cycle. This phantom read (reading ahead) by the PCI9060ES affects target devices that
change their data or state upon access, such as FIFOs or other devices. (For example, some
devices de-assert their interrupts after a vector is read.) In these cases, the PCI9060ES phan-
tom read access can result in a bus error or bad data upon subsequent read cycles.
Hex Address:
Bits:
Register Field:
Factory Default Value (hex):
C100,0094
3:0
Direct Slave BREQo Delay Clocks
1 (8 clocks)
C100,0094
4
Local Bus BREQo Enable
1 (BREQo enabled)
C100,0098
31:28
PCI Target Retry Delay Clocks
F (120 clocks)