Epson S1D13504 Manuel D’Utilisation
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Epson Research and Development
Vancouver Design Center
S1D13504
Interfacing to the Philips MIPS PR31500/PR31700 Processor
X19A-G-005-08
Issue Date: 01/02/02
The Generic MPU host interface control signals of the S1D13504 are asynchronous with
respect to the S1D13504 bus clock. This gives the system designer full flexibility in
choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether
both clocks should be the same and whether to use DCLKOUT (divided) as the clock
source, should be based on the desired:
respect to the S1D13504 bus clock. This gives the system designer full flexibility in
choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether
both clocks should be the same and whether to use DCLKOUT (divided) as the clock
source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.