Epson S1D13504 Manuel D’Utilisation
Page 86
Epson Research and Development
Vancouver Design Center
S1D13504
Hardware Functional Specification
X19A-A-002-18
Issue Date: 01/01/30
7.4.13 CRT Timing
Figure 7-39: CRT Timing
VDP
= Vertical Display Period
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
VNDP
= Vertical Non-Display Period
= (REG[0Ah] bits [5:0]) + 1
HDP
= Horizontal Display Period
= ((REG[04h] bits [6:0]) + 1)*8Ts
HNDP
= Horizontal Non-Display Period
= HNDP
1
+ HNDP
2
= ((REG[05h] bits [4:0]) + 1)*8Ts
VRTC
HRTC
LINE1
LINE480
1-1
1-2
1-640
HRTC
DACCLK
BLANK#
DACP[7:0]
DACD[7:0]
VDP
HDP
VNDP
HNDP
1
BLANK#
Example Timing for 640x480 CRT
HNDP
2
LINE480