Siemens ERTEC200 Manuel D’Utilisation
2.9.1
Prioritization of Interrupts
It is possible to set the priorities of the IRQ and FIQ interrupts. Priorities 0 to 15 can be assigned to IRQ interrupts while
priorities 0 to 7 can be assigned to FIQ interrupts. The highest priority is 0 for both interrupt levels. After a reset, all IRQ
interrupt inputs are set to priority 15 and all FIQ interrupt inputs are set to priority 7. A priority register is associated with
each interrupt input. PRIOREG0 to PRIOREG15 are for the IRQ interrupts and FIQPR0 to FIQPR7 are for the FIQ
interrupts. A priority must not be assigned more than once. A check for the assignment of identical priorities is not
performed in the ICU logic. All interrupt requests with a lower or equal priority can be blocked at any time in the IRQ
priority resolver by assigning a priority in the LOCKREG register. If an interrupt that is to be blocked is requested at the
same time as the write access to the LOCKREG register, an IRQ signal is output. However, the signal is revoked after
two clock cycles. If an acknowledgement is to be generated nonetheless, the transferred interrupt vector is the default
vector.
priorities 0 to 7 can be assigned to FIQ interrupts. The highest priority is 0 for both interrupt levels. After a reset, all IRQ
interrupt inputs are set to priority 15 and all FIQ interrupt inputs are set to priority 7. A priority register is associated with
each interrupt input. PRIOREG0 to PRIOREG15 are for the IRQ interrupts and FIQPR0 to FIQPR7 are for the FIQ
interrupts. A priority must not be assigned more than once. A check for the assignment of identical priorities is not
performed in the ICU logic. All interrupt requests with a lower or equal priority can be blocked at any time in the IRQ
priority resolver by assigning a priority in the LOCKREG register. If an interrupt that is to be blocked is requested at the
same time as the write access to the LOCKREG register, an IRQ signal is output. However, the signal is revoked after
two clock cycles. If an acknowledgement is to be generated nonetheless, the transferred interrupt vector is the default
vector.
2.9.2 Trigger
Modes
The “Edge-triggered” and “Level-triggered” operating modes are available for each interrupt input.
The trigger type is defined by means of the assigned bit in the TRIGREG register. For the “Edge-triggered” mode setting,
differentiation can be made between a positive and negative edge evaluation. This is made in the EDGEREG register. In
“Level-triggered” mode, the active level of the interrupt request is high active. By default, the IRQ interrupt parameters
are assigned as described in Section 2.9.7, and the FIQ interrupts parameters are assigned as described in Section
2.9.8.
In “Edge-triggered” mode, the interrupt input signal must be present for at least one clock cycle. In “Level-triggered”
mode, the input signal must be present until the ARM946E-S CPU is confirmed. Shorter signals result in loss of the
event.
The trigger type is defined by means of the assigned bit in the TRIGREG register. For the “Edge-triggered” mode setting,
differentiation can be made between a positive and negative edge evaluation. This is made in the EDGEREG register. In
“Level-triggered” mode, the active level of the interrupt request is high active. By default, the IRQ interrupt parameters
are assigned as described in Section 2.9.7, and the FIQ interrupts parameters are assigned as described in Section
2.9.8.
In “Edge-triggered” mode, the interrupt input signal must be present for at least one clock cycle. In “Level-triggered”
mode, the input signal must be present until the ARM946E-S CPU is confirmed. Shorter signals result in loss of the
event.
2.9.3
Masking the Interrupt Inputs
Each IRQ interrupt can be enabled or disabled individually. The MASKREG register is available for this purpose. The
interrupt mask acts only after the IRREG interrupt request register. That is, an interrupt is entered in the IRREG register
in spite of the block in the MASKREG register. After a reset, all mask bits are set and, thus, all interrupts are disabled. At
a higher level, all IRQ interrupts can be disabled globally via a command. When IRQ interrupts are enabled globally via a
command, only those IRQ interrupts that are enabled by the corresponding mask bit in the MASKREG register are
enabled.
For the FIQ interrupts, only selective masking by the mask bits in the FIQ_MASKREG register is possible. After a reset,
all FIQ interrupts are disabled. A detected FIQ interrupt request is entered in the FIQ interrupt request register. If the
interrupt is enabled in the mask register, processing takes place in the priority logic. If the interrupt request is accepted
by the ARM946 CPU and an entry is made in the in-service request register (ISR), the corresponding bit is reset in the
IRREG register. Each bit that is set in the IRREG register can be deleted via software. For this purpose, the number of
the bit to be reset in the IRCLVEC register is transferred to the interrupt controller.
interrupt mask acts only after the IRREG interrupt request register. That is, an interrupt is entered in the IRREG register
in spite of the block in the MASKREG register. After a reset, all mask bits are set and, thus, all interrupts are disabled. At
a higher level, all IRQ interrupts can be disabled globally via a command. When IRQ interrupts are enabled globally via a
command, only those IRQ interrupts that are enabled by the corresponding mask bit in the MASKREG register are
enabled.
For the FIQ interrupts, only selective masking by the mask bits in the FIQ_MASKREG register is possible. After a reset,
all FIQ interrupts are disabled. A detected FIQ interrupt request is entered in the FIQ interrupt request register. If the
interrupt is enabled in the mask register, processing takes place in the priority logic. If the interrupt request is accepted
by the ARM946 CPU and an entry is made in the in-service request register (ISR), the corresponding bit is reset in the
IRREG register. Each bit that is set in the IRREG register can be deleted via software. For this purpose, the number of
the bit to be reset in the IRCLVEC register is transferred to the interrupt controller.
2.9.4
Software Interrupts for IRQ
Every IRQ interrupt request can be triggered by setting the bit corresponding to the input channel in the software
interrupt register SWIRREG. Multiple requests can also be entered in the 16-bit SWIRREG register. The software
interrupt requests are received directly in the IRREG register and, thus, treated like a hardware IRQ. Software interrupts
can only be triggered by the ARM946E-S processor because only it has access authorization to the interrupt controller.
interrupt register SWIRREG. Multiple requests can also be entered in the 16-bit SWIRREG register. The software
interrupt requests are received directly in the IRREG register and, thus, treated like a hardware IRQ. Software interrupts
can only be triggered by the ARM946E-S processor because only it has access authorization to the interrupt controller.
2.9.5
Nested Interrupt Structure
When enabled by the interrupt priority logic, an IRQ interrupt request causes an IRQ signal to be output. Similarly, an
FIQ interrupt request causes the FIQ signal to be output to the CPU.
When the request is accepted by the CPU, the bit corresponding to the physical input in the register ISRREG is set. The
IRQ/FIQ signal is revoked. The ISR bit of the accepted interrupt remains set until the CPU returns an End-Of-Interrupt
command to the interrupt controller. As long as the ISR bit is set, interrupts with lower priority in the priority logic of the
interrupt controller are disabled. Interrupts with a higher priority are allowed by the priority logic to pass and generate an
IRQ/FIQ signal to the CPU. As soon as the CPU accepts this interrupt, the corresponding ISR bit in the ISRREG register
is also set. The CPU then interrupts the lower-priority interrupt routine and executes the higher interrupt routine first.
Lower-priority interrupts are not lost. They are entered in the IRREG register and are processed at a later time when all
higher-priority interrupt routines have been executed.
FIQ interrupt request causes the FIQ signal to be output to the CPU.
When the request is accepted by the CPU, the bit corresponding to the physical input in the register ISRREG is set. The
IRQ/FIQ signal is revoked. The ISR bit of the accepted interrupt remains set until the CPU returns an End-Of-Interrupt
command to the interrupt controller. As long as the ISR bit is set, interrupts with lower priority in the priority logic of the
interrupt controller are disabled. Interrupts with a higher priority are allowed by the priority logic to pass and generate an
IRQ/FIQ signal to the CPU. As soon as the CPU accepts this interrupt, the corresponding ISR bit in the ISRREG register
is also set. The CPU then interrupts the lower-priority interrupt routine and executes the higher interrupt routine first.
Lower-priority interrupts are not lost. They are entered in the IRREG register and are processed at a later time when all
higher-priority interrupt routines have been executed.
2.9.6 EOI
End-Of-Interrupt
A set ISR bit is reset by the End-Of-Interrupt command. The CPU must communicate this to the interrupt controller with
the EOI command after processing of the corresponding interrupt server routine. To communicate the EOI command to
the interrupt controller, the CPU writes any value to the IRQEND/FIQEND registers. The interrupt controller decides
independently which ISR bit will be reset with the EOI command. If several ISR bits are set, the interrupt controller
deletes the ISR bit of the highest-priority interrupt request at the time of the EOI command. The interrupt cycle is
considered complete for the interrupt controller when all set ISR bits have been reset by the corresponding number of
EOI commands. After this, lower-priority interrupts that have occurred in the meantime and have been entered in the
RREG register can be processed in the priority logic.
During one or more accepted interrupts, the priority distribution of the IRQ/FIQ interrupt inputs must not be changed
because the ICU can otherwise no longer correctly assign the EOI commands.
the EOI command after processing of the corresponding interrupt server routine. To communicate the EOI command to
the interrupt controller, the CPU writes any value to the IRQEND/FIQEND registers. The interrupt controller decides
independently which ISR bit will be reset with the EOI command. If several ISR bits are set, the interrupt controller
deletes the ISR bit of the highest-priority interrupt request at the time of the EOI command. The interrupt cycle is
considered complete for the interrupt controller when all set ISR bits have been reset by the corresponding number of
EOI commands. After this, lower-priority interrupts that have occurred in the meantime and have been entered in the
RREG register can be processed in the priority logic.
During one or more accepted interrupts, the priority distribution of the IRQ/FIQ interrupt inputs must not be changed
because the ICU can otherwise no longer correctly assign the EOI commands.
Copyright © Siemens AG 2007. All rights reserved.
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ERTEC 200 Manual
Technical data subject to change Version 1.1.0